1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor integrated circuit device. More particularly, the invention relates to a structure of a semiconductor device adapted for preventing electrostatic discharge damage, which is to be formed as an output circuit of a semiconductor integrated circuit device.
2. Description of the Related Art
An example of semiconductor devices, which are conventionally known as the above type of semiconductor device, includes: a gate electrode formed, via a gate insulating layer, on a semiconductor layer of a silicon substrate; an impurity diffused layer formed on a semiconductor layer of an active region and forming a source region or a drain region; and contact areas formed on a gate electrode present in the active region, and does not include a silicide layer on the impurity diffused layer (see, for example, Japanese Patent Application Laid-Open (JP-A) No. 2001-189429, p. 1, FIG. 3).
By connecting the gate electrode to a metal wiring layer, which is disposed above and along the gate electrode, at a plurality of points via the contact areas, an apparent gate resistance can be reduced. However, a stress is generated when the contact areas for connection are formed on the gate electrode. In order to avoid the stress affecting the gate insulating layer, and in order to prevent the gate insulating layer from being damaged by etching, a pad-like insulating layer is provided under the gate electrode at areas where the contact areas are formed. Therefore, the structure becomes complicated and this complicates the layout design.
Technical backgrounds for the invention will be described below in more detail.
In recent years, development of SOI (Silicon On Insulator) devices, which are excellent in accomplishing high-speed LSIs and low power consumption, are progressing. For producing the SOI devices, a SALICIDE (Self-Aligned Silicide) process is particularly favored. The salicide process is a technique of forming silicide, which is a compound of silicon and a metal, on an impurity diffused layer and polysilicon.
FIGS. 5A and 5B show a structure of a main portion of a salicide NMOS transistor 100 created on a SOI substrate. FIG. 5A is a plan view, and FIG. 5B is a sectional view of the main portion taken along line A—A in FIG. 5A.
The NMOS transistor is fabricated by a MOS process on the SOI substrate, which includes a buried oxide film 102 on a P semiconductor substrate 101.
Low resistance silicides 106, 107 and 108 are respectively formed on impurity diffused layers formed of a source (or drain) region 103 and a drain (or source) region 104, as well as on a gate electrode 105 formed of polysilicon. An interlayer insulating layer 115 is formed over the silicides, and contacts 116, which connect the silicides 106 and 107 to metal wiring (not shown) formed on the interlayer insulating layer 115, are formed in the interlayer insulating layer 115.
Usually, such a salicide transistor is very weak to ESD (Electro-Static Discharge). This is because that a surge current due to ESD flows through the low resistance silicide layer which lies above the drain or source, and a stress of a heavy-current after breakdown concentrates at a PN junction surface region 110 or 111, and therefore, junction breakdown is likely to be caused. This surge current is generated in the following mechanism.
In a case of a NMOS transistor, for example, when a positive surge voltage due to ESD is applied to the drain, breakdown is caused between the drain region (N+) and the body region (P−). Then, holes are accumulated in the body region and a potential at the body region is raised. As the potential at the body region is raised beyond a potential barrier at the PN junction between the body region (P−) and the source region (N+), a parasitic NPN bipolar transistor, formed of the drain region (N+)—the body region (P−)—the source region (N+), is turned on and the ESD surge current flows from the drain to the source as a bipolar current.
In order to prevent element breakdown caused by ESD, salicide block-type NMOS transistors have been proposed. FIGS. 6A and 6B show a structure of a main portion of a salicide block NMOS transistor 130. FIG. 6A is a plan view, and FIG. 6B is a sectional view of the main portion taken along line B—B in FIG. 6A. It should be noted that elements which are substantially common with those of the salicide NMOS transistor 100 in FIGS. 5A and 5B are designated by the same reference numerals.
The salicide block NMOS transistor 130 is a transistor which is produced such that, when the silicide is formed, a salicide block is formed at a salicide block area 139, which includes the gate electrode 105 and partial areas of a source (drain) 133 and a drain (source) 134 in the vicinity of the gate electrode 105, so that the silicide is not formed in this area.
With this structure, the surge current due to ESD does not concentrate at a portion in the impurity diffused layer and flows relatively uniformly so that electric field concentration is not caused. Further, a resistor component in the impurity diffused layer, at areas of the drain and the source where the silicide is not formed thereon, causes a drop in the high ESD surge voltage, and the stress applied to the PN junction is reduced. Thus, ESD resistance is remarkably improved.
The salicide block area is provided so as to extend to both of the drain and the source. This is because that, unlike to a process using a bulk substrate, where no breakdown is caused at a PN junction at a source side when potentials at a well and at the source are the same, in a SOI device having a complete element isolation structure using a buried oxide film and a field oxide film, PN junction breakdown may be caused by breakdown at the source side depending on a polarity of the ESD surge. The same applies to a PMOS transistor.
The salicide block transistor having excellent ESD resistance, as described above, is used, for example, as a final output transistor in a LSI which operates as a semiconductor integrated circuit device. FIG. 8 is a circuit diagram of a main portion showing a position, in a circuit configuration, of a salicide block NMOS transistor 144 used as a final output transistor in an output circuit in an LSI 140.
As shown in FIG. 8, the salicide block NMOS transistor 144 forms, together with a salicide block PMOS transistor 143, a push-pull output circuit, where a drain is connected to an output terminal 142 of the LSI 140. Further, a protective circuit 141 is provided in a wiring path connecting the drain to the output terminal 142.
With this structure, the salicide block transistors 143 and 144, which have excellent ESD resistance, are not broke down even when an ESD surge is applied to the output terminal 142. While, transistors in an internal circuit 145 are protected by the protective circuit 141. Therefore, salicide MOS transistors, such as shown in FIGS. 5A and 5B described above, can be used for forming the internal circuit 145.
FIGS. 7A and 7B show an exemplary structure of the salicide block NMOS transistor 144 shown in the circuit diagram of FIG. 8. FIG. 7A is a plan view, and FIG. 7B is a sectional view of a main portion taken along line C—C in FIG. 7A.
As shown in FIGS. 7A and 7B, the NMOS transistor is fabricated on a SOI substrate by a MOS process. The SOI substrate includes silicon 152 having a buried oxide film therein, formed on a P semiconductor substrate 151 serving as an insulating layer.
During a silicide forming process, no silicide is formed on partial areas of an impurity diffused layer formed of a source (or drain) region 154 and drain (or source) regions 153 and 155, as well as on polysilicon gate electrodes 158 and 159 formed on body regions 156 and 157 via oxide films 160 and 161, because of salicide blocks formed in salicide block areas 162a and 162b, and low resistance silicides 170, 171 and 172 are respectively formed in only areas other than these areas.
An interlayer insulating layer 163 is formed over the silicides. Further, on top of the interlayer insulating layer 163, drain (source) metal wiring 164, source (drain) metal wiring 165 and gate metal wiring 167 are formed. The drain (source) metal wiring 164 includes a connecting portion 164a extending along the silicide 170, a connecting portion 164b extending along the silicide 172, and a coupling portion 164c coupling the connecting portions 164a and 164b together. The source (drain) metal wiring 165 extends along the silicide 171. The gate metal wiring 167 electrically couples the two gate electrodes 158 and 159 with each other.
Further, the interlayer insulating layer 163 is provided with contacts 175 for electrically connecting the silicide 170 to the connecting portion 164a at a plurality of points, contacts 176 for electrically connecting the silicide 172 to the connecting portion 164b at a plurality of points, contacts 177 for electrically connecting the silicide 171 to the source (drain) metal wiring 165 at a plurality of points, and contacts 178 for electrically connecting the two gate electrodes 158 and 159 to the gate metal wiring 167. As described above, the salicide block NMOS transistor 144 used as the final output transistor here has a structure where two salicide block transistors having a large gate width W are arranged in parallel with each other.
By making the transistors having a large gate width W into the salicide block transistor, since resistance of polysilicon of the gate electrodes is large at portions of the gate electrodes which are far from the gate metal wiring 167, to which a gate signal is connected, a very large gate resistance, which is equivalent to a resistor 147, is inevitability inserted. For a device requiring high-speed operation, increase in a gate delay time at the final output transistor has to be avoided.
Therefore, although it is ideal for the salicide block NMOS transistor 144 shown in FIGS. 7A and 7B to have a structure where the low resistance silicide layer is formed only on the gate electrodes 158 and 159, considering an accuracy of masking of the salicide block and the gate electrodes, the silicide layer is inevitably formed also on a part of the drain or source in the vicinity of the gate electrodes 158 and 159, and this lowers ESD resistance. It should be noted that, as a measure against this, a method for reducing the gate resistance without forming the silicide layer on the gate electrodes is disclosed in the above-cited JP-A No. 2001-189429.
The present invention is made on the above-described technical background, and solves the above-described prior-art problems.